The present invention relates to an apparatus and method for providing clock edges for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality.
Precision delay line circuits requiring the real-time programming of delay line values every clock cycle have required restrictive rules of operation. For example, new delay values are only allowed to increase from one cycle to another, or specific delay values are not allowed. These rules have placed limitations on conventional delay line circuits. Accordingly, a need exists for improvements in precision delay line circuits.
A clock control circuit consistent with the present invention is used for loading delay data into delay circuits. It includes a clock enabled latch receiving an enable signal and a delay line signal. A latch receives the delay line signal and an output of the clock enabled latch. A multiplexer, receiving the output of the clock enabled latch and being controlled by an output of the latch, provides a signal to load delay data in response to the enable signal and the delay line signal.
Another clock control circuit consistent with the present invention is used for loading delay data into delay circuits. It includes an input for receiving an enable signal and a delay line signal, and an output for outputting a delayed clock signal having first and second states. A control circuit provides an enabled state with the delayed clock signal in the first state and an output state with the delayed clock signal in the second state. The control circuit switches between the enabled state and the output state in response to first and second edges of the delay line signal.
A method consistent with the present invention provides signals for use in loading delay data into delay circuits. It includes receiving an enable signal and a delay line signal, and outputting a delayed clock signal having first and second states. An enabled state is provided with the delayed clock signal in the first state, and an output state is provided with the delayed clock signal in the second state. Switching between the enabled state and the output state occurs in response to first and second edges of the delay line signal.